The invention generally relates to phase-locked loops that generate a clock synchronized in phase with an input signal and more particularly to improving phase-locked loops applicable to zone bit recording in hard disk systems, etc.
As shown in FIG. 4, prior art configurations widely used for phase-locked loops in data separators and frequency multiplier circuits for magnetic disk devices, etc., comprise, a phase comparator 10 which compares the phases of an input signal S.sub.IN, a reference signal, and an oscillator output V.sub.OUT (at oscillation frequency f.sub.OSC) of a voltage-controlled oscillator 40, and outputs first and second phase difference detection signals X.sub.1 and X.sub.2. A charge pump 20 supplies a charge/discharge current i (pulse output current) to a loop filter 30 capacitor C.sub.F which is based on the first and second phase difference detection signals X.sub.1 and X.sub.2. Loop filter 30 is a low pass filter (LPF) which is configured as a series circuit including resistor R.sub.F and capacitor C.sub.F, and voltage-controlled oscillator (VCO) 40 which generates oscillator output V.sub.OUT at oscillation frequency f.sub.OSC, which corresponds to a value for analog filter output voltage V.sub.F, which is used as a control input.
Voltage-controlled oscillator 40 generally comprises a voltage-current conversion circuit, which converts the control input voltage into a current, and a current-frequency conversion circuit which changes the frequency f.sub.OSC of oscillator output V.sub.OUT, according to the resulting output current. Oscillation frequency f.sub.OSC of voltage-controlled oscillator 40 may be input into phase comparator 10 using a prescribed divider. Phase comparator 10 is a digital phase comparator; e.g., configured from a pair of D-type flip-flops and a logic gate. Charge pump 20, as shown in FIG. 5, is a series circuit configured from a switching transistor 22 (p-type MOSFET) used for source current switching, which turns ON when first phase difference detection signal X.sub.1 is at a low level, a constant current source 24 used to generate source current; a switching transistor 26 (n-type MOSFET) used for sink current switching, which turns ON when second phase difference detection signal X.sub.2 is at a high level, and a constant current source 28 used to generate sink current.
When a phase difference occurs in oscillator output V.sub.OUT with respect to input signal S.sub.IN in a phase-locked loop having the above configuration, phase comparator 10 generates phase difference detection signals X.sub.1, X.sub.2. Charge pump 20 outputs source or sink current i using signals X.sub.1, X.sub.2, as shown in FIG. 6. Therefore, a voltage drop is generated across resistor R.sub.F of filter 30 and capacitor C.sub.F is charged and discharged by this pulse current. Since oscillation frequency f.sub.OSC of voltage-controlled oscillator 40 is varied by the value of the filter output voltage V.sub.F, the phase difference between oscillator output V.sub.OUT and input signal S.sub.IN becomes zero as time progresses.
During a time in which signals X.sub.1, X.sub.2 of each period are not generated, an integrated load is stored in capacitor C.sub.F, and, therefore, the output of voltage-controlled oscillator 40 is controlled by that charging voltage. Therefore, the charging voltage of capacitor C.sub.F for current i functions as a frequency control signal for the pull-in operation that matches oscillation frequency f.sub.OSC to the frequency of input signal S.sub.IN. The voltage drop in resistor R.sub.F for current i functions as a phase control signal for the lock-in operation since it controls the output phase of voltage-controlled oscillator 40, when error signals X.sub.1, X.sub.2 are generated.
Since this kind of phase-locked loop performs phase locking with respect to a specific input signal S.sub.IN which fluctuates within a narrow frequency range, the value of the electrical element of each circuit is optimized. These include, for example, the value of output current i of charge pump 20, the time constant of loop filter 30, and the conversion factor for the output frequency of the voltage-controlled oscillator 40 with respect to the input voltage. Therefore, in zone bit recording in a hard disk system, input signal S.sub.IN is generated, for example, at data transfer rates of four zones (f.sub.1 =8 MHz, f.sub.2 =10 MHz, f.sub.3 =12 MHz, f.sub.4 =14 MHz) in which the data transfer rate is switched, but since the frequency component for jitter also changes, it is necessary to perform an adjustment that optimizes the values of the above circuit elements at the points of change. More specifically, it is necessary to provide a plurality of loop filters with differing time constants, and to switch and connect to the optimum loop filter in synchronization with the switching of the frequency of the input signal.
The two equations below are important equations for describing the basic characteristics (phase difference characteristics) of a phase-locked loop that uses loop filter 30 as shown in FIG. 5. ##EQU1##
Here, w.sub.n is the natural angular frequency, z is the damping factor, K.sub.v is voltage frequency conversion factor of voltage-controlled oscillator 40, K.sub.c is the phase comparator conversion factor that matches phase comparator 10 and charge pump 20, C is the electrostatic capacitance of capacitor C.sub.F of loop filter 30, and R is the resistance value of resistor R.sub.F of loop filter 30. Natural angular frequency w.sub.n must change in proportion to the frequency for quick lock-in when the frequency (data transfer rate) of input signal S.sub.IN is high, but it is generally necessary to make damping factor z a constant value (e.g., 2.sup.-1/2 .apprxeq.0.7). This is important from the standpoint of the phase step response and peak shift margin characteristics of the phase-locked loop. Because of its circuit configuration, voltage-controlled oscillator 40 has fixed voltage frequency conversion factor K.sub.v, and, therefore, cannot be easily changed from outside the circuit. Therefore, when the data transfer rate is changed, w.sub.n can be made proportional to the data transfer rate while z remains constant by making K.sub.c proportional to the data transfer rate, making C inversely proportional to the data transfer rate and making R constant. Here, K.sub.c is generally displayed in radians and is given by i/2p. Therefore, if output current i is made proportional to the data transfer rate by switching the internal circuit, factor K.sub.c becomes proportional to the data transfer rate, and, therefore, current sources 24 and 28 must be configured as variable current sources.
However, the phase-locked loop described above which uses a filter comprising a resistor and a capacitor presents the following problems.
(1) When the data transfer rate is fast, output current i of charge pump 10 must be made large, the value of capacitor C.sub.F of filter 30 must be made small. By comparison, when the data transfer rate is slow, the voltage drop of resistor R.sub.F and the charge voltage of capacitor C.sub.F become extremely large when output current i is generated. For this reason, the dynamic range is narrow because output voltage V.sub.F of filter 30 is readily clipped by the power source voltage. Therefore, the higher the data transfer rate, the narrower the pull-in range.
(2) When the above phase-locked loop is configured as an integrated circuit (IC) chip, the following problems are encountered. That is, plural loop filters configured as series circuits of C and R must be attached externally to the IC chip, and selection of an optimum loop filter synchronized with the switching of the data transfer rate. But when output current i is supplied to external loop filter 30 from charge pump 20 built into the IC chip, the value of output current i must be large.
This is because a requisite parasitic capacitance is generated in the wiring path from the charge pump inside the IC to the external loop filter (output cell, bonding wire, lead frame, etc.) or in the opposite wiring path from the loop filter to the voltage-controlled oscillator 40 inside the IC. Therefore, charge pump 20 must generate a somewhat large output current in consideration of the amount of charge consumed by the parasitic capacitance. This output current must be made larger as its frequency range increases more than the low frequency range. This is because as the data transfer rate changes to a higher frequency range, the pulse duration of phase difference detection signals X.sub.1, X.sub.2 becomes shorter and the drive time of charge pump 20 becomes smaller; e.g., in the case of a 50 MHz input signal S.sub.IN, the drive time drops to less than 20 ns. Therefore, it is necessary to set the output current to a value with a larger margin in anticipation of the charge consumed by the parasitic capacitance. In order for the charge pump to generate this kind of large output current, it is necessary to use large MOS transistors to form current sources 24, 28 and to use large (gate width) switching transistors 22, 26 so that their ON resistance is small and current capacity is large.
This increased transistor size naturally promotes increased parasitic capacitance between the gate and the drain, and the so-called feed through effect of the gate signal extending to the output terminal becomes larger, resulting in waveform distortion due to disturbance of the rectangular waveform of the loop filter drive current. Also, since there is an increase in the gate capacitance accompanying the increased gate area, which is a natural result of the increased transistor size, a gate signal with a pulse duration of several nanoseconds is consumed by the gate capacitance, thus making the ON/OFF operation of the transistor difficult when a gate signal is impressed. When a switching speed of several nanoseconds becomes impossible, the resolution of phase locking becomes irregular. In other words, phase locking is poor within the high frequency range. Further, though a pulse type output current i is supplied to the external loop filter, the pulse type output current itself contains a considerable high frequency component, and, therefore, as the pulse duration becomes shorter, a wiring inductance component manifests itself, which greatly disturbs the output current waveform and tends to destabilize the input voltage of voltage-controlled oscillator 40, resulting in poor phase locking stability.
The invention solves the above problems. First, it offers a phase-locked loop capable of making the phase difference between the input signal and the output signal zero even when the frequency of the input signal, which is the reference signal, changes discretely or continuously. Secondly, it offers a phase-locked loop with a wide pull-in range even in phase-locking operations for input signals of any frequency. Thirdly, it offers a phase-locked loop with superior phase locking resolution, and phase locking in high frequency ranges while also having good phase-locking stability.